发明名称 ANALOG FIFO MEMORY
摘要 PROBLEM TO BE SOLVED: To read out accurately a written analog signal by eliminating an error of the analog signal at the time of write-in and read-out as an analog FIFO memory. SOLUTION: A memory bus circuit 1 is provided with a plurality of memory cells 10 storing an analog signal, and a memory bus 13 connected to each memory cell 10 and transferring the analog signal. Further, the memory bus circuit 1 is provided with a dummy memory cell 120 having a dummy capacity element 121 connected to the memory bus 13. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005209342(A) 申请公布日期 2005.08.04
申请号 JP20050113807 申请日期 2005.04.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MICHIMASA SHIRO;YANAGISAWA NAOSHI;KURIMOTO HIDEHIKO
分类号 G11C7/00;(IPC1-7):G11C7/00 主分类号 G11C7/00
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