| 摘要 |
PROBLEM TO BE SOLVED: To provide such a demodulation method and a demodulator that, after a data series of continuous binaries is converted to an input data word of a 4 bits unit, it can be converted to an output code word train of a 6 bits unit satisfying 7≤k≤12 with a (1, k) RLL (run length limited) rule and also a DSV control can be performed without adding a redundant bit to the output code word train, and a DC component of the output code word train is effectively suppressed and the continuation of a shortest bit inversion is suppressed. SOLUTION: The suppression of the DC component under limitation of k=7 or 8 is performed by using an encoding table which can convert 4 bits into 6 bits with the (1, k) RLL rule without using redundant bits. A phase synchronization for extracting a clock which is used at the demodulation is facilitated by interrupting the continuation of the shortest bit inversion. COPYRIGHT: (C)2005,JPO&NCIPI
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