发明名称 ARITHMETIC CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an arithmetic circuit device capable of high speed calculation of an ND value having many required parameter lower bits used in the Montgomery product sum remainder calculation. SOLUTION: The ND value generator section 11 creates the value of the required lower bits of the ND value by each k bit from the lower bits in a single clock cycle by referring to the value of lower k bits of a variable Sum and the value of lower k bits of a positive odd number value N. The product sum calculation section 12 adds the variable Sum to the product of the value of the k bits of the created ND value and the positive odd number value N of the lower bits. The Sum value storage section 13 updates the value obtained by k bit right shifting the calculated result of the product sum calculation section 12 as the variable Sum to use in the next clock cycle in the ND value generator section 11 and stores it. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005208498(A) 申请公布日期 2005.08.04
申请号 JP20040017206 申请日期 2004.01.26
申请人 FUJITSU LTD 发明人 MUKODA KENJI;TAKENAKA MASAHIKO;TORII NAOYA;MASUI SHOICHI
分类号 G06F7/72;G09C1/00;(IPC1-7):G09C1/00 主分类号 G06F7/72
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