发明名称 |
HIGH RESOLUTION PHASE LOCKED LOOP |
摘要 |
A phase locked loop (PLL) generates a phase locked signal and adjusts a frequency of the phase locked signal according to an incoming signal. The PLL includes an oscillator for generating the phased locked signal and a frequency detection module electrically coupled to the oscillator. The frequency detection module includes a pattern detector for detecting the two regular patterns in the incoming signal, a counter electrically coupled to the pattern detector for calculating the number of periods of the phase locked signal corresponding to the distance between the two regular patterns, and a comparator electrically coupled to the counter for comparing the number of periods with a predetermined value to generate a control signal, and using the control signal to control the oscillator to adjust the frequency of the phase locked loop signal.
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申请公布号 |
US2005168254(A1) |
申请公布日期 |
2005.08.04 |
申请号 |
US20040710894 |
申请日期 |
2004.08.11 |
申请人 |
HOU KUEN-SUEY;YANG JIN-BIN |
发明人 |
HOU KUEN-SUEY;YANG JIN-BIN |
分类号 |
G11B5/09;G11B20/14;H03L7/085;H03L7/087;H03L7/113;(IPC1-7):G11B5/09 |
主分类号 |
G11B5/09 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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