Three-dimensional semiconductor package, and spacer chip used therein

摘要

In a three-dimensional semiconductor package, a logic-circuit chip has a plurality of top electrode terminals formed on a top surface thereof, and a spacer chip is mounted on the logic-circuit chip. The spacer chip has a plurality of bottom electrode terminals formed on a bottom surface thereof, and a plurality of top electrode terminals formed on a top surface thereof and electrically connected to the respective bottom electrode terminals thereof. The mounting of the spacer chip on the logic-circuit chip is carried out such that the bottom electrode terminals of the spacer chip are bonded to the top electrode terminals of the logic-circuit chip, to thereby establish electrical connections therebetween. A memory chip is mounted on the spacer chip, and has a plurality of electrode terminals formed on a surface thereof. The mounting of the memory chip on the spacer chip is carried out such that the electrode terminals of the memory chip are bonded to the top electrode terminals of the spacer chip, to thereby establish electrical connections therebetween.