| 摘要 |
PURPOSE:To prevent a drop in an action efficiency and to guarantee contents in a memory by allowing an access right giving decision means to prevent the access right from being given to other CPUs in spite of outputting an access right request signal from other CPUs if one CPU accesses to a shared memory. CONSTITUTION:An address bus from each CPU communicates with the shared memory 1 through bus buffers 2 and 4, while bus buffers 3 and 5 are installed on a data bus between each CPU and the shared memory. The access right request signal M from a master CPU and a recognition signal Sm from an access right control circuit are inputted to the input terminal of an AND circuit 6, and its output terminal is connected to the enable terminals E of the bus buffers 4 and 5. On the other hand the access right request signal S from a slave CPU and a recognition signal Ss from the access right control circuit are inputted to the one input terminal of an AND circuit 7, and its output terminal is connected to the enable terminals E of the bus buffers 2 and 3. |
