发明名称 ARITHMETIC AND LOGIC UNIT
摘要 PURPOSE:To efficiently execute MAD operation, etc., at a high speed with a less number of steps, by adding a control circuit to be used for making specific operation with a less number of instruction steps to a control section. CONSTITUTION:Connections among an arithmetic and logic operator 31, status register 33, and register R3 are made in such a way that the output of one status register SRB is given to the ALU controller 41 of the operator 31 as shown in the figure. This ALU controller 41 is prepared by adding a control circuit shown in figure 3 to conventional one. The control circuit is to be used for controlling the 'addition (ADD)', 'subtraction (SUB)', and 'no operation (NOP)' in MAD operation and formed to a logic circuit, through which the ALU controller 41 can or cannot lead out a prescribed output depending upon the outputting state of the status register SRB and register R3. Therefore, specific operation of MAD operation, etc., can be executed in a less number of steps by the action of the control circuit.
申请公布号 JPS62257526(A) 申请公布日期 1987.11.10
申请号 JP19860102792 申请日期 1986.04.30
申请人 MITSUBISHI ELECTRIC CORP 发明人 ANDO HIDEKI;MACHIDA HIROHISA
分类号 G06F7/00;G06F7/575 主分类号 G06F7/00
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