| 摘要 |
PURPOSE:To curtail the number of gates by developing simultaneously plural logical expressions to a Karnaugh map, detecting an overlapping part between the logical expressions, and collecting them to one. CONSTITUTION:A logic optimization processing method consists of an integration possibility inspection processing part, a logical expression Karnaugh map development processing part, and an overlapping logic integration processing part. The integration possibility inspection processing part selects plural pieces of logical expressions which have been stored in a logical expression store table, and inputs them to this processing part. In this case, the logical expression whose possibility of integration is high, among plural pieces of logical expressions is selected. Subsequently, a group of the logical expressions which have been decided that the integration property is high, by the integration possibility inspection processing part is developed to a Karnaugh map by the logical expression Karnaugh map development processing part. In this case, in plural Karnaugh maps, the same signal names are made to occupy the same position on the Karnaugh map. Subsequently, in the overlapping logic integration processing part, the logical expressions corresponding to a part where '1' is set in common on the obtained Karnaugh map are collected to one as an overlapping logical expression. In this way, the overlapping parts of each logical expression are unified.
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