发明名称 INTERPOLATION ENLARGEMENT ARITHMETIC CIRCUIT
摘要 PURPOSE:To obtain an interpolation enlargement arithmetic circuit for outputting enlarged image information in various interpolation enlargement methods by at least one piece of arithmetic processing circuit, by constituting said circuit so that a kind of its arithmetic operation can be controlled by a control circuit without limiting an interpolation enlargement arithmetic operation. CONSTITUTION:An arithmetic designating signal for designating an arithmetic processing is applied to an arithmetic processing circuit 1 from a controlling circuit 2. By this designating signal, the arithmetic circuit 1 executes an interpolation enlargement processing to an input image data Dn for constituting (m)X(n) picture elements, and outputs an interpolation enlarged image data On for constituting MXN images. For instance, when the circuit is constituted in advance so that segmenting of 4X4 picture elements and the arithmetic operation can be executed, an interpolation enlargement arithmetic operation in 2X2 picture elements, 3X3 picture elements, and 4X4 picture elements can be executed optionally, and also, an interpolation enlarging circuit which can execute optionally its arithmetic processing is obtained.
申请公布号 JPS63683(A) 申请公布日期 1988.01.05
申请号 JP19860142932 申请日期 1986.06.20
申请人 FUJITSU LTD 发明人 NAGAOKE TAKAO
分类号 G06T3/40 主分类号 G06T3/40
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