| 摘要 |
PURPOSE:To prevent the production of a large power noise by giving a signal being the result of a delay given to a data signal or its inverted signal by means of a delay means by a prescribed time as one input respectively to two multi-input logic circuits giving a gate input to a P-channel and an N-channel transistors (TRs) for output so as to suppress a through-current. CONSTITUTION:With a data signal D changed from a high level to a low level, an output point (a) of a NAND gate 11 goes to a high level as soon as a level of the data signal D is lower than its logic threshold value. On the other hand, a level of an output point (b) of a NOR gate 12 goes to a high level with a delay by a delay time after the input of a delay means DL goes to a low level till the output goes to a low level. Thus, the operation of the N-channel TR TN going from the off-state to the on-state so far is started slowly more than the operation of the P-channel TR TP from the on-state so far to the off-state and a through-current is decreased. Similarly, when the data signal D changes from a low level to a high level, the through-current is decreased by the reversing operation in comparison with that above. |
