| 摘要 |
PURPOSE:To prevent lower gate thin film voltage withstanding and hot electron withstanding capabilities from deterioration by a method wherein a lower layer is built of amorphous silicon, the layer is subjected to patterning, a high-melting metal layer is formed, and then a heat treatment process is accomplished for the development of the high-melting metal on the amorphous silicon into a silicide. CONSTITUTION:A gate thermal oxide SiO2 film 2 is formed on a silicon substrate 1, an amorphous silicon layer 3 is formed by spattering or low- temperature CVD, and the layer 3 is subjected to patterning. A titanium layer 4 is formed by spattering or CVD, and a heat treatment is done for the formation of a TiSi2 layer 5 on the amorphous silicon layer 3 only. A part of the titanium layer 4 not experiencing reaction is removed from the SiO2 film 2 by using an RCA liquid for the formation of a titanium polyside layer consisting of the amorphous silicon layer 3 and TiSi2 layer 5. In a flat silicide layer resulting from reaction between titanium and amorphous silicon, titanium does not reach a gate thermal oxide SiO2 film 2. Accordingly, a titanium polyside layer may be formed wherein a gate thin film is protected from degrading.
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