发明名称 METHOD FOR FORMING WIRING IN SEMICONDUCTOR DEVICE
摘要 PURPOSE:To construct a high-accuracy wiring pattern by a method wherein a first spacer layer to be affected not easily by wet etching and a second spacer layer to be affected easily by wet etching are in that order formed on a substrate and then dry etching is accomplished in compliance with a prescribed resist pattern. CONSTITUTION:SiN films are formed under different conditions on a substrate 1. For example, a first spacer layer 2 to be affected not easily by wet etching, a second spacer layer 3 to be affected easily by wet etching, and a resist patter 4, are formed on the substrate 1, in that order. The resist pattern 4 serves as a mask in a process of dry etching whereby the two spacer layers 2 and 3 are vertically etched. After this, the second spacer layer 3 only is subjected to a wet side-etching process. A prescribed thickness of wiring metal is provided by evaporation, and a wiring pattern 5 is formed in an opening in the first spacer layer 2. In this way, a high-accuracy wiring pattern is built, not affected by resist sagging.
申请公布号 JPS63122244(A) 申请公布日期 1988.05.26
申请号 JP19860269293 申请日期 1986.11.12
申请人 SUMITOMO ELECTRIC IND LTD 发明人 ISHII MANABU
分类号 H01L21/3205 主分类号 H01L21/3205
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