| 摘要 |
PURPOSE:To stabilize the operation of a reception circuit by using an add number parity to the added bit, and connecting another gate supplying the output of an exclusive OR and its inverted output to the output of the gate, to prevent mis-detection as input disconnection. CONSTITUTION:A data of mB1P code adding 1-bit odd parity to a data comprising m-bit of '1' and '0' and a clock are inputted to an AND circuit 1. The output of the gate 3 is supplied to one input of a gate 5 feeding the output of an exclusive OR and the inverted output of the exclusive OR to one input, the output of the exclusive OR of the gate 5 is branched, the one is fed to a low pass filter 8 and the other is fed to the other input of the gate 5 via a delay circuit 6 retarding the input by (m+1)-bit and the output of the inversion of the output of the exclusive OR of the gate 5 is fed to a low pass filter 7. Thus, the unstable clock recovery due to consecutive '0's in the data system or mis-detection of input disconnection are prevented so as to accurately ensure the operation of the reception circuit.
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