| 摘要 |
PURPOSE:To attain of the title device fining and the reduction of junction capacitance by properly controlling the film thickness of an anti-oxidizing film and forming a graft base region in a self-alignment manner. CONSTITUTION:An SiO2 film 108 and an Si3N4 film 106 are etched, using a CVD-SiO2 film pattern 110 as a mask, and an Si3N4 film 111 is shaped onto the whole surface as an anti-oxidizing film and etched in an anisotropic manner. An epitaxial layer 104 is etched, employ. ing the pattern 110 and the film 11 as masks. An SiO2 film 112 is formed, and an Si3N4 film 114 is shaped, and etched in the anisotropic manner. An SiO2 film 116 is formed, and the films 111, 114 are removed. The film 116 is used as an insulating film for element isolation. The films 112 and 116 are etched in the anisotropic manner, and the junction section of a base leading-out electrode and the layer 104 is exposed. A poly Si film 118 is shaped onto the junction section as a conductive material film. Accordingly, the area of the junction section is determined by the film thickness of the film 111, thus resulting in fining, then reducing junction capacitance.
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