| 摘要 |
PURPOSE:To reduce jitter, and to improve a high fidelity characteristic by providing a second PLL circuit to perform the correction processing of the jitter of a signal demodulated by a first PLL circuit, and obtaining a synchronizing signal by frequency-dividing the oscillation output of a high fidelity oscillator. CONSTITUTION:The first phase-locked loop circuit(PLL circuit) A is constituted of a phase comparator 4 and a voltage controlled oscillator 5, and outputs the synchronizing signal of a wide band including the sampling frequencies of more than two kinds, for the digital interface signals of more than two kinds to be received by a receiving part 1. Further, this circuit is provided with a control circuit 6 to receive the output of the receiving part 1, the phase comparator 7, a frequency divider 8 and the high stability oscillator 9, and those constitute the second PLL circuit B. Here, when sampling frequency information is obtained, the output signal of the high stability oscillator 9 is divided by the frequency divider 8 according to the instruction of the control circuit 6, and the synchronizing signal of the frequency very close to the frequency of the digital interface signal is outputted. Thus, the data with less jitter is obtained. |
