| 摘要 |
PURPOSE:To realize an array structure suited to the high-speed arithmetic and also to an integrated form by securing such a constitution where the addition results of the unit circuit groups divided in response to the higher and lower rank digit partial product groups respectively are centralized. CONSTITUTION:The AND circuits 1a and 1b of the first stage of unit circuit groups 7 and 8 calculate each corresponding partial product respectively. The result of said calculations are given to the sum signal 5 to half adders 2a and 2b of the second stage respectively. The adders 2a and 2b add those signals 5 to each partial product and the results of these calculations are given to full adders 3a and 3b of the third stage as the signal 5 and the carry signal 6 respectively. Hereafter the calculation is carried out in the same way up to the final stage. Then both signals 5 and 6 obtained from each final stage are totalized every same digits via a unit circuit group 4. Thus the final result of multiplication is obtained. In such a constitution, it is possible to realize an array structure that has the natural signal transmission direction and is suited to an integrated form. |
