MEMORY ADDRESSING ERROR DETECTION CIRCUIT

摘要

PURPOSE: To prevent a write operation to a read-only area by providing a hash generation device for generating a hash value from an address from an I/O unit and a comparison device for comparing the address with the hash value. CONSTITUTION: When the commanded I/O unit transfers data to a main memory 10 or receives them from the memory 10, an I/O processor 55 places a real main memory address on a bus 14. The low-order bit of the address of an address register 20 is gated to an I/O hash generation logic device 26 and the device 26 generates a hash. An I/O hash bit from the device 26 is compared with a high-order hash bit in the register 20 by a comparison logic device 27. When the generated hash bit does not match with the hash bit from the register 20, error conditions are present and signals for indicating the conditons are sent through an error line 28 to the I/O unit. The signals indicate that the address sent to the the processor for data transfer is invalidated.