| 摘要 |
A speed correction circuit for use in a modem implementing a data communications protocol having tighter tolerances on bit timing for the transmitted data than for the input data. Selective insertion and deletion of stop bits is used to compensate for overspeed or underspeed conditions between the input and the transmitted data streams. The apparatus loads the incoming data into a FIFO register of predetermined length. Counters in a clock circuit keep track of character timing. Just before transmission of a stop bit, predetermined positions in the FIFO are tested to see if they are occupied in order to detect an overspeed or underspeed condition. If no overspeed or underspeed is detected the top bit is transmitted in its normal fashion. If underspeed is detected, a transmit controller sends a stop bit, and shifting out of the last bit in the FIFO is suppressed for one bit time. This inserts a stop bit in the data stream while allowing additional bits to come into the FIFO. If overspeed is detected, the stop bit then present at the output of the FIFO is shifted out prior to the transmit controller being clocked to send out the bit then present on the FIFO output. This shifts out the stop bit and allows the first bit from the next character to ripple through to the output prior to clocking of the transmit controller, thus deleting a stop bit from the transmitted data stream to correct the overspeed condition.
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