发明名称 Sample and hold circuit for temporal associations in a neural network
摘要 A sample and hold circuit for introducing delayed feedback into an associative memory is described. The circuit continuously samples an output sequence derived from a neural network; then, in response to a clock signal, it holds that output sequence until the next clock signal. The held sequence is coupled back to the input of the network so that the present output sequence becomes some function of the past output sequence. This delayed feedback enables the associative recall of a memorized sequence from the neural network.
申请公布号 US4906865(A) 申请公布日期 1990.03.06
申请号 US19880282636 申请日期 1988.12.09
申请人 INTEL CORPORATION 发明人 HOLLER, MARK A.
分类号 G06G7/60;G06F15/18;G06N3/04;G06N99/00;G11C11/54;G11C15/00;G11C15/04;G11C27/02 主分类号 G06G7/60
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