| 摘要 |
PURPOSE:To lower parasitic inductance by connecting a wiring board, at a central section of which an opening section for arranging an integrated circuit chip is formed, and the integrated circuit chip positioned in the opening section of the wiring board by a connecting material. CONSTITUTION:A wiring board 9 has multilayer structure in which metallic layers and ceramic layers 9A are laminated in multilayers, and signal conductors 14 and a power supply line 18 are shaped. An opening section 13 slightly larger than a semiconductor IC chip 5 is shaped at a chip loading position at a center in the wiring board 9, and the terminal sections of the signal conductors 14 and the power supply line 18 and the semiconductor IC chip 5 are connected as short as possible to connecting materials 10. That is, the height of the bonding terminals of the signal conductor sections and the height of upper connecting terminals in the capacitor 15 of the power supply line section are aligned in the height of the bonding pads of the semiconductor IC chip 5 in the wiring board 9, and the opening section 13 is scaled down as much as possible, thus shortening the connecting materials 10. Consequently, parasitic inductance can be lowered. The wiring board is formed in multilayer structure, thus reducing impedance. |
