发明名称 DATA CONVERSION CIRCUIT FROM TIME DIVISION SYSTEM INTO PACKET SYSTEM USING FIRST-IN FIRST-OUT MEMORY
摘要 <p>PURPOSE:To decrease the capacity of a buffer memory and to attain the efficient packet processing by using a first-in first-out memory, thereby attaining the packet processing sequentially from the line of the buffer memory whose data storage exceeds one packet. CONSTITUTION:A time division multiplex control means 1 selects a data from a time division multiplex bus based on line assignment location information and fetches it to a buffer memory 2 for each line, and a packet selection means 3 monitors the data quantity at every line in the buffer memory 2 to input the data sequentially from a line capable of applying packet processing to a first-in first-out memory 4. Thus, it is possible to read the data from the buffer memory 2 and the packet selection means 3 at the high speed and to allow the first-in first-out memory 4 to receive the data. Thus, the capacity of the buffer memory 2 is reduced and the efficient packet processing is attained.</p>
申请公布号 JPH02280439(A) 申请公布日期 1990.11.16
申请号 JP19890102133 申请日期 1989.04.20
申请人 FUJITSU LTD 发明人 NOGUCHI TOSHIHIRO
分类号 H04L12/56 主分类号 H04L12/56
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