| 摘要 |
A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop and a bit loading element. The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element is connected to receive the flip-flop output and a bit input of a multibit number being loaded and to provide a bit output of the counter, the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit. |
