SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PURPOSE:To reduce restrictions on a scan design by making the design of scanning timing easier and preventing the occurrence of malfunctions at time of switching modes. CONSTITUTION:Scan storing elements 111-114 and a mode select terminal 104 which switches operations between ordinary operations and scanning operations are provided. Since a delay element 110 is provided on a testing clock signal line 140, a time lag is produced between a testing clock signal and ordinary clock signal and, even when the signal to an external input terminal 103 is switched from the testing clock signal to the ordinary clock signal before switching the operating mode from the scanning mode to the ordinary mode, the testing clock signal reaches after the signal is delayed from the signal of the terminal 103 by the delay time caused by the delay element 110.