发明名称 Locos isolation scheme for small geometry or high voltage circuit
摘要 A process and for fabricating field oxide isolation pattern with field implants associated therewith that can be used for increasingly smaller dimensional elements, for example in feature sizes of 0.8 micrometers or less, and simpler processing than the prior art is described. A semiconductor substrate is provided. A multilayer oxidation masking structure of a thin silicon oxide layer, a silicon nitride layer, and a polycrystalline silicon layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and the polycrystalline silicon layer from the areas designated to have field oxide isolation grown therein to form a narrow opening. The structure is exposed to an oxidizing environment such that the polysilicon oxide layer forms an "overhang" over part of the field isolation region. Ion implanting in a vertical direction is accomplished to form the field implant in the silicon surface of the dimension of the narrow opening less the overhang. The polysilicon oxide layer is removed. The field oxide insulator structure is grown by subjecting the structure to oxidation whereby the field implant is confined under the field oxide isolation and not encroaching the planned source/drain implant regions.
申请公布号 US5208181(A) 申请公布日期 1993.05.04
申请号 US19920930367 申请日期 1992.08.17
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING PTE LTD. 发明人 CHI, KEH-FEI C.
分类号 H01L21/266;H01L21/32;H01L21/762 主分类号 H01L21/266
代理机构 代理人
主权项
地址