发明名称 COEFFICIENT DATA REVISION PROCESSING SYSTEM FOR DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To have a time margin in the processing and to eliminate the need for high-speed operation by writing coefficient data stored in a transfer buffer to a coefficient data memory through read cycle steal in the read instruction processing cycle of the coefficient data. CONSTITUTION:Whether or not a read instruction is an instruction for coefficient data to implement read cycle steal is discriminated based on a count of a program counter 15. When the instruction is the read instruction, new coefficient data to be revised by an instruction read stage and an instruction decoding stage are transferred from a microcomputer 20 to a transfer buffer 18. Then the coefficient data stored in the buffer 18 are written in a coefficient data memory 9 through the read cycle steal at the execution stage of the read instruction processing cycle of the coefficient data. Thus, the new coefficient data to be rewritten in the instruction execution stage have only to be written to a relevant address position of the coefficient data RAM 9. Thus, the processing time of coefficient data rewrite at the read cycle steal has a margin and no high speed operation is required.
申请公布号 JPH05167395(A) 申请公布日期 1993.07.02
申请号 JP19910335260 申请日期 1991.12.18
申请人 PIONEER VIDEO CORP;PIONEER ELECTRON CORP 发明人 SUDO SHUHEI;YAMAKI MAKIO
分类号 G06F9/38;G06F9/24;G06F9/312;G10K15/12;H03H17/00;H03H17/02 主分类号 G06F9/38
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