DISPOSITIVO DI MEMORIA A SEMICONDUTTORE CON STRUTTURA A TRIPLA ZONA A POZZETTO

摘要

An integrated semiconductor RAM memory cell array region (100) and peripheral circuit region (400) incorporates a triple well structure comprising a first n-type well (22, 81) formed in a p-type substrate (70) and biased by a first bias voltage (Vcc), a p-type well (23, 83) formed in the first well and biased by a second bias voltage (Vbb), and a further n-type well, which is a region of an MOS transistor, formed in the p-type well and connected to the second bias voltage. The substrate may be arranged to receive a third bias voltage.