| 摘要 |
Applicable to digital data transmission systems. Based on generating control signals in the flexible memory 1 which indicate when information is repeated or lost, making possible the control of alignment circuits such that a drift in the flexible memory 1 owing to frequency differences between the reception clock and the transmission system does not necessarily entail misalignment when the alignment stage is reached. For this, there is provided a stage of generation of FRAME signals, consisting of a flexible memory 1, a reading counter 2, a writing counter 3, a comparator and control block 4, which generates said FRAME signals, and a PIPO circuit S; there being connected to this stage a multiframe signalling alignment circuit, associated with the channel for a frame G.704 of 2,048 kbit per second or an alignment circuit per recommendation X.50 for channel intervals of 64 kbit per second contained in a frame G.704 of 2,048 kbit per second, all of this being designed according to the method of the invention. <IMAGE>
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