INTEGRIERTER HALBLEITERSPEICHER MIT PARALLELTESTMOEGLICHKEIT UND REDUNDANZVERFAHREN.

摘要

An integrated semiconductor memory includes a parallel test device and block groups. The parallel test device is used for writing in and evaluating data to be written into and read out of the semiconductor memory. Several groups of memory cells can be simultaneously tested for operation in a test mode, with each group being disposed along a respective word line. The data read out during the process can be evaluated by the parallel test device. The result of the evaluation is present, separately for each group of memory cells, on I/O data lines of the semiconductor memory. The semiconductor memory can also have redundant memory cells, in which case defective memory cells or groups of memory cells can be replaced in connection with the test mode.