SEMICONDUCTOR MEMORY APPARATUS

摘要

A semiconductor memory device is provided to prevent damage to a semiconductor memory device or a test device due to a TDBI(Test During Burn-In) process by performing a stress test using a multi pattern with a wafer state in a limited environment after packaging in the TDBI process. A first refresh control part(320) counts an address, and generates a row address corresponding to an output of a test pattern generating part in a built-in self stress test. A second refresh control part(330) counts an address, and generates a column address and a bank address corresponding to an output of the test pattern generating part in the built-in self stress test. A test decoder(340) decodes a signal inputted through a plurality of address pads, and outputs a test control signal for controlling a test or a built-in self stress test performed in a wafer state. The test pattern generating part(380) generates a test pattern about a plurality of inner operations corresponding to an output of the test decoder. A test command address generating part(390) generates an inner test command and an inner address signal corresponding to an output of the test pattern generating part.