| 摘要 |
A cache memory is provided to minimize the access failure of the cache memory by reducing access time delay of word line. A low decoder(10) decodes/outputs an inputted address signal. A word line voltage controller is connected to the output lines of the low decoder on one-to-one basis. In case the output signal outputted through the output line of the low decoder is the enable signal, a plurality of word line voltage control logics(50) of the word line voltage controller outputs the basis voltage signal corresponding to the voltage level of the enable signal. In other words, a plurality of word line voltage control logics outputs the enforcement voltage signal corresponding to the voltage level higher than the basis voltage signal. It is controlled by the basis voltage signal or the enforcement voltage signal, a word line driver(20) activates word lines.
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