摘要 |
A semiconductor memory device includes transistors that supply a higher write potential and a lower write potential to a sense amplifier, respectively, an overdrive transistor that supplies an overdrive potential to the sense amplifier, and a control circuit that changes a gate-source voltage of the overdrive transistor step by step. By raising a potential of one of paired bit lines to the overdrive potential not suddenly but step by step, an influence of a potential increase on the other bit line via a parasitic capacity is lessened and a malfunction caused by data inversion is prevented.
|