发明名称 |
Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) |
摘要 |
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
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申请公布号 |
US7576668(B2) |
申请公布日期 |
2009.08.18 |
申请号 |
US20070934611 |
申请日期 |
2007.11.02 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
UDUPA ANAND HARIRAJ;SINHA VIKAS KUMAR;AGARWAL NITIN;PENTAKOTA VISVESVARARAYA A.;OSWAL SANDEEP |
分类号 |
H03M1/00 |
主分类号 |
H03M1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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