发明名称 |
Semiconductor integrated circuit including memory macro |
摘要 |
The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.
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申请公布号 |
US7577882(B2) |
申请公布日期 |
2009.08.18 |
申请号 |
US20070998602 |
申请日期 |
2007.11.30 |
申请人 |
PANASONIC CORPORATION |
发明人 |
KURUMADA MAREFUSA;AKAMATSU HIRONORI |
分类号 |
G11C11/413;G11C29/00;G11C29/04 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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