| 摘要 |
The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs-InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiOx-cladded Si quantum dots can also be used as high-k dielectric layer forming the gate insulator over the transport channel of a sub-22 nm FET.
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