| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce test time for repair analysis of a memory device or on-chip analysis of failure diagnosis without increasing a hardware scale. <P>SOLUTION: An on-chip failure information analysis circuit 100 comprises a memory device 102A in which data is stored, a built-in self test unit 101 which drives the memory device 102A, a failure detection unit 102B for detecting a failure of memory output of the memory device 102A, a failure information storage unit 103B for storing the failure information including a location of the failure, an failure information analysis unit 103A which performs failure analysis using the number of failures detected by the failure detection unit 102B and the location of the failure to write the failure information including the analysis result in the failure information storage unit 103b, and an analysis result output unit 103C which outputs the analysis result of the failure information analysis unit 103A. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
