| 摘要 |
A delay lock loop circuit and a phase lock loop circuit are designed to reduce a lock-up time, extend a lock range without increasing the number of bits of a counter, and quickly return to a lock target upon deviation from the lock target. There are provided with a plurality of phase comparators 11a, 11b, counters 12a, 12b, and DA converters 13a, 13b. A resolution per unit bit of each of the DA converters 13a, 13b is differentiated. An adder element 14 adds up delay times indicated by delay time signals output from the DA converters 13a, 13b, and a BIAS 15 converts a sum of the delay times into delay times of delay elements of a delay element group 16 and supplies it to an output signal.
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