发明名称 |
Wiring layer fill structures |
摘要 |
<p>Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures (30a, 30b, 30c, 30d) are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures (30a) are formed near wiring regions (26a) having high aspect ratio wiring structures and larger fill structures (30d) are located near wiring regions (26d) with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect r atio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.
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申请公布号 |
EP1463109(A3) |
申请公布日期 |
2009.07.22 |
申请号 |
EP20040101010 |
申请日期 |
2004.03.11 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BORST, CHRISTOPHER L.;TSAO, ALWIN, J.;STRONG, BOBBY, D.;RUSSELL, NOEL |
分类号 |
H01L21/3205;H01L21/768;H01L21/3105;H01L21/321;H01L21/82;H01L23/522 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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