| 摘要 |
It is known that fast, fully combinational leading-digit detector circuits (also known as priority encoders) can be generated efficiently by recognizing their inherent hierarchical structur e. It is shown herein that this structure is not only hierarchical, but also recursive. This recursivity fully defines a minimal-complexity circuit, thus garanteeing optimal circuit synthesis. Such a circuit having an N-bit operand generates all output bits with log2(N) combinational stages. It also makes possible a recursive parametenzable description in VHD L or other hardware description languages supporting recursion. For standard cell generation, it is amenable to efficient, automatic recursive routing. Furthermore, the same recursive structure can serve as the basis of other useful arithmet ic functions, including fast adder structures, fast incrementers / decrementers and a fast comparator. Therefore, this multifunction circuit could be employed in the design of fast, low-complexity arithmetic-logic units (ALUs) inside microprocessors, digital signal processors, or application-specific system-on-chip (SoC) designs. By selective applicati on of power to various subtrees, the multifunction circuit also provides low-power benefits in addition to economies in logic area (with respect to separate implementation of the various functions)
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