发明名称 |
Device and method for limiting Di/Dt caused by a switching FET of an inductive switching circuit |
摘要 |
A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt. An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.
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申请公布号 |
US7564292(B2) |
申请公布日期 |
2009.07.21 |
申请号 |
US20070864686 |
申请日期 |
2007.09.28 |
申请人 |
ALPHA & OMEGA SEMICONDUCTOR, INC. |
发明人 |
HAVANUR SANJAY |
分类号 |
H03K17/04 |
主分类号 |
H03K17/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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