发明名称 Bistable flip-flop having retention circuit for storing state in inactive mode
摘要 A bistable flip-flop device is provided that is triggered on the edges of a clock signal. The device has an active mode in which it is electrically powered and an inactive mode. The device includes a chain of inverters controlled by a clock signal, storage means for storing the state of the device in the active mode, and retention means for storing the state of the device in the inactive mode. The device includes a continuously-powered bistable structure that integrates the retention means and part of the storage means. The bistable structure includes a single isolation switch connected to the inverter chain and controlled by a standby logic signal that is representative of the active or inactive mode.
申请公布号 US7564282(B2) 申请公布日期 2009.07.21
申请号 US20050258826 申请日期 2005.10.26
申请人 STMICROELECTRONICS SA 发明人 CLERC SYLVAIN
分类号 H03K3/289 主分类号 H03K3/289
代理机构 代理人
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