发明名称 Fast parity scan of memory arrays
摘要 A novel method for scanning bit parity in a memory array, and a circuit for implementing it, are disclosed. In a memory array that has one or more rows of memory cells, the method for checking data parity includes storing a plurality of data bits in the memory cells, scanning a row of memory cells independently of a memory read operation to ascertain the stored data bits; and determining parity for the row of memory cells by the results of the scanning. The method is accomplished by means of a dedicated parity scanning circuit.
申请公布号 US7565597(B1) 申请公布日期 2009.07.21
申请号 US20050315971 申请日期 2005.12.21
申请人 INTEGRATED DEVICE TECHNOLOGY, INC. 发明人 BRANTH KENNETH;PARK KEE W.
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
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