发明名称 |
Chip and wafer integration process using vertical connections |
摘要 |
A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.
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申请公布号 |
US7564118(B2) |
申请公布日期 |
2009.07.21 |
申请号 |
US20080114145 |
申请日期 |
2008.05.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
POGGE H. BERNHARD;YU ROY;PRASAD CHANDRIKA;NARAYAN CHANDRASEKHAR |
分类号 |
H01L23/12;H01L29/40;H01L21/44;H01L21/68;H01L21/768;H01L23/48;H01L23/485;H01L23/52;H01L23/525;H01L25/065;H01L25/07;H01L25/18 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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