发明名称 BUILT-IN JITTER MEASUREMENT CIRCUIT
摘要 A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.
申请公布号 US2009096439(A1) 申请公布日期 2009.04.16
申请号 US20070870113 申请日期 2007.10.10
申请人 FARADAY TECHNOLOGY CORP. 发明人 HSU JEN-CHIEN;LU HUNG-WEN;SU CHAU-CHIN;CHANG YEONG-JAR
分类号 G01R29/26;G01R23/12 主分类号 G01R29/26
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