| 摘要 |
PROBLEM TO BE SOLVED: To increase test speed by dispensing with a lock-up time when switching a mode. SOLUTION: In this semiconductor integrated circuit device loaded with a PLL unit 1, for testing in a scan shift mode and in a capture mode by using an output clock of the PLL unit as a testing clock, the PLL unit 1 has a constitution equipped with the first frequency divider 11 for generating the first clock CLK 1 to be used in the scan shift mode by dividing an input clock CLK from the outside with the first frequency-division number K, the second frequency divider 12 for generating the second clock CLK 2 by dividing the input clock CLK with the second frequency-division number M, and a PLL 14 for receiving the second clock and generating the third clock CLK 3 to be used in the capture mode. COPYRIGHT: (C)2009,JPO&INPIT
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