发明名称 |
A SCALABLE SCAN-PATH TEST POINT INSERTION TECHNIQUE |
摘要 |
A logic circuit comprising at least one input, one output and a delay fault circuit. The delay fault circuit includes a first standard scan cell, a combinational test point positioned immediately after the first standard scan cell in a scan chain and a second standard scan cell positioned immediately after the combinational test point in the scan chain. |
申请公布号 |
WO2004102803(A3) |
申请公布日期 |
2009.04.16 |
申请号 |
WO2004US04354 |
申请日期 |
2004.02.12 |
申请人 |
NEC LABORATORIES AMERICA, INC. |
发明人 |
WANG, SEONGMOON;CHAKRADHAR, SRIMAT |
分类号 |
G06F17/50;G01R31/3183;G01R31/3185 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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