发明名称 |
SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS |
摘要 |
Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
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申请公布号 |
US2009100122(A1) |
申请公布日期 |
2009.04.16 |
申请号 |
US20080324055 |
申请日期 |
2008.11.26 |
申请人 |
ALTERA CORPORATION |
发明人 |
ZHENG LEON;LANGHAMMER MARTIN;PERRY STEVEN;METZGEN PAUL;PRASAD NITIN;HWANG WILLIAM |
分类号 |
G06F7/38;G06F7/499;G06F7/52;G06F7/523;G06F7/544 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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