| 摘要 |
Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, a chip-wide PCT processing operation is performed on the semiconductor chip layout for a given chip level. The presence of the PCT pre-processed cells in the semiconductor chip layout serves to accelerate the chip-wide PCT processing of the semiconductor chip layout. The chip-wide PCT processed semiconductor layout for the given chip level is recorded on a persistent storage medium.
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