| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit highly accurately controlling the frequency of an output clock signal. <P>SOLUTION: The phase-locked loop circuit has: a capacity 104 for storing a control voltage; a phase detector 101 for detecting the difference in phase between a feedback signal and a reference clock signal; first switches SW1, SW2 for connecting the capacity to a power supply voltage or a reference potential depending on the detected phase difference; a voltage controlled oscillator 105 for generating an output clock signal of an oscillation frequency corresponding to the control voltage of the capacity, and outputting the output clock signal or a signal corresponding to the output clock signal as a feedback signal to the phase detector; and a second switch circuit SW3 for connecting the capacity to the reference voltage or the power supply voltage for a predetermined period from the edge of the reference clock signal and for a predetermined period from the edge of the output clock signal or the signal corresponding to the output clock signal. <P>COPYRIGHT: (C)2009,JPO&INPIT |
