发明名称 SEMICONDUCTOR PACKAGE
摘要 A semiconductor package is provided to partially limit a useless dummy region by forming a dummy lead on a position of a substrate corresponding to an align key formed on a semiconductor chip. A semiconductor package includes a semiconductor chip(110), a substrate(120), an align key(113), and a dummy lead(123). The semiconductor chip is extracted from a disk type wafer. Terminals(111) connected to an electronic circuit device are protruded from one surface of the semiconductor chip. A lead(121) and a pattern corresponding to the terminals are formed on a top of the semiconductor chip. The substrate is adhered to the semiconductor chip by a lead on chip method or a flip chip method. The align key is formed on a top of the semiconductor chip. The dummy lead is formed on an edge position corresponding to the align key.
申请公布号 KR20090037558(A) 申请公布日期 2009.04.16
申请号 KR20070102925 申请日期 2007.10.12
申请人 STECO, LTD. 发明人 YOON, SUK BUM;SUNG, KI JUN;JEON, JE SEOG
分类号 H01L23/495 主分类号 H01L23/495
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