| 摘要 |
A nonvolatile semiconductor memory for suppressing the access delay due to the parasitic capacitance between bit lines is disclosed. Bit lines are selected by a bit select signal, and the data of the memory cell selected in accordance with the level of data lines by a sense amplifier are read, after which the read data are held in a latch circuit. Then, a control signal is set to "High", thereby to turn on a NMOS and set the data lines to a grounding potential. As a result, the charges of the selected bit lines are discharged. After that, even if adjacent bit lines are selected next for reading, the effect of the parasitic capacitance between the adjacent bit lines is obviated, and the next data can be read without causing any access delay.
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